1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having an array of variable resistive elements of two-port structure type and particularly to a resistance controlling method of applying a voltage pulse to the two ports of a variable resistive element of interest to change the resistance characteristic of the variable resistive element.
2. Description of the Related Art
There will be an epoch where desired data can be obtained and kept at any time and any location. As mobile devices such as mobile telephones or PDAs (portable, personal data communication devices) have been spread in the market, they allow various data to be accessed with no limitations of time and location. However, the primary functions of such mobile devices including the life of batteries and the speed of access to data remain not high enough to be satisfied and will hence be demanded for much improvement. In particular, while the life of batteries is one of the essential requirements which determine the utilization of a mobile device, the power consumption for components in the mobile device has to be significantly minimized.
One of the key devices for satisfying the foregoing requirement is a non-volatile semiconductor memory. When such a mobile device is active in motion, its logic circuit for conducting logic functions may be predominant in the power consumption. In a standby mode, the power consumption of a memory device may be increased most. It is not negligible that the power consumption at the standby mode disturbs the lengthening of the life of batteries in a mobile device. The supply of power to a memory device in the standby mode may be eliminated when the memory device is replaced by a non-volatile semiconductor memory which can minimize the power consumption at the standby mode.
Such non-volatile semiconductor memories include flash memories and FeRAMs (ferroelectric random access memories) which have already been introduced in the market. Those memories have however trade-off relationships between the high-speed operation, the durability to write actions, the power consumption, and other primary properties. Further actions of research and development of ideal non-volatile semiconductor memories are now on the way for satisfying all the requirements.
As some expedient non-volatile semiconductor memories employing new materials have been proposed, one of them is a resistance random access memory (RRAM) which comprises an array of non-volatile memory elements of the variable resistance type (variable resistive elements), each element having a layer structure of a lower electrode, a metal oxide, and an upper electrode, so that the electric resistive characteristic is reversibly varied between the lower electrode and the upper electrode when an electrical stress is applied to between the same. Since RRAM is highly potential to improve the operational speed, the storage size, and the energy saving, its advantages will be expected in the future.
A variable resistive element for use in RRAM is disclosed in “Novel colossal random access memory (RRAM)” by Zhuang, H. H., et al, IEDM, Article No. 7.5, December 2002, (will be referred to as Citation 1) which has a perovskite crystalline structure made of a manganese oxide material, namely Pr1·XCaXMnO3 (0<x<1, abbreviated to as PCMO) to gain the characteristics of colossal magnetoresistance (CMR) and high temperature super conductivity (HTSC) and arranged to be applied with a voltage pulse for modifying the resistance.
The resistance modifying property of the variable resistive element is practically denoted by a profile shown in FIG. 21 where the vertical axis represents the resistance and the horizontal axis represents the number of applications of pulses when the PCMO layer at 100 nm of thickness is applied with a 100 nanoseconds voltage pulse of ±5 V. Upon the application of pulses, the resistance is varied between 1 kΩ and 1 MΩ as reversed more than 100 times within a range of three digits. Also as shown in a profile of FIG. 22 where the vertical axis represents the resistance and the horizontal axis represents the number of applications of a 5 nanoseconds voltage pulse at 4 V, the resistance of the variable resistive element is varied in steps depending on the number of applications of the voltage pulse. The resistance changes not only between two levels, a low resistance level (for example, not higher than 1 kΩ) and a high resistance level (for example, not lower than 100 kΩ), but also among any desired number of different levels between the two extremes. For example, the resistance states may represent four different levels between 10 kΩ and 1 MΩ as shown in FIG. 23 as remaining low in the bit cost. When having an array of the described variable resistive elements as memory cells, a non-volatile semiconductor memory device can be improved in the operational speed and the storage size.
Also for increasing the storage size of an RRAM device, an attempt has been made as disclosed in “Evaluation of SiO2 antifuse in a 3D-OTP memory” by Feng Li et al, IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3 (2004), pp. 416-421 (referred to as Citation 2), where arrays of memory cells are arranged vertically in layers on a substrate surface to increase the storage size per unit area and minimize the production cost per bit. The three dimensional semiconductor memory device of Citation 2 is hence a non-volatile OTP memory device which has a 3D structure in which arrays of the memory cells are arranged vertically in layers on the substrate for permitting one time of the program action. More specifically, the memory cell arrays of cross-point type in which each memory element is located at the intersection between a word line and a bit line are placed one over another in the vertical to construct a four-layer structure.
The memory device of Citation 2 has the layers of its memory cells made of polycrystalline silicon. The memory cell area per bit is commonly 4 F2. The unit “F” is the minimum of measurement to be used in the production process. The memory device is equal in the memory cell area to a flash memory which employs the same design rules. Since the 3D semiconductor memory device has a four-layer structure of the memory cell arrays, the memory cell area is practically ¼ of the size 4 F2, or 1 F2. Accordingly, the memory device is smaller in the production cost than the flash memory. Each memory cell in the memory cell arrays comprises a state variable region called an antifuse and a diode as the selectable region connected in series to each other and is connected at its two ends to a word line and a bit line, respectively. The antifuse is provided in the form of a silicon oxide layer while the diode is provided in the form of a layer stack of p-type silicon and n-type silicon. The storage of a data is based on a change in the resistance of the antifuse when the memory cell is applied with a voltage. The antifuse remains at higher level of insulating state in the initial state and can be turned to a conductive state when receiving a voltage higher than the threshold. Once the antifuse is shifted to the conductive state, it will not return back to the insulating state, thus allowing one time of the program action. The diode is connected for inhibiting a leak current across a memory cell to be selected.
When an RRAM is structured by the above described 3D memory cell structure, its readout action can be improved in the repeatability and the utilization but its write action can not be performed (by programming and erasing) with the use of a voltage of two, positive and negative, polarities because of the rectifying property of the diode. Another attempt has hence been proposed as disclosed in “Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses” by I. G. Baek et al, IEDM Technical Digest, December 2004, pp. 587-590 (referred to as Citation 3) which employs a mono-polar switching technology in which the write action is performed by modifying the pulse width of the voltage pulse to be applied to the variable resistive element (RRAM element) in the memory cell for programming or erasing so as to distinguish the program action and the erase action. Accordingly, the resultant non-volatile semiconductor memory device having memory cells with the rectifying property and the cross-point type memory cell array structure can electrically be written while remaining increased in the storage size.
It is however necessary for carrying out the mono-polar switching action over each variable resistive element to shift the variable resistive element from its initial state after the production to a variable resistance state through application of a forming voltage pulse. For example, the memory device of Citation 3 is applied with a forming voltage pulse which is higher than that of the program and erase action in order to develops a current path such as a filament in its variable resistive element which remains not conductive at the initial state after the production.
However, there is no satisfactory solution over the relationship between the condition for applying the forming voltage pulse to shift from the initial state to the variable resistance state for enabling the mono-polar switching action and the resistant property in the variable resistance state. The condition for applying the voltage pulse to conduct the erase action and the program action in the mono-polar switching action when the forming voltage pulse has been applied has to be set to an optimum depending on the characteristic of each sample.